Climbing up the Career Ladder

時間83() 15:45-17:15

簡介這次論壇的主題為 “Climbing Up the Career Ladder"。 半導體產業除了極富挑戰性外,也有非常多不同的發展機會。 研究生當如何規劃?如何把握機會?如何找到自己的路向?如何準備自己可以在未來發展得更高更遠? 這次論壇我們邀請到五位在半導體產業各有專精的先進,來分享他們從研究生到職場的成功經驗。 他們當中除了有選擇加入大家所熟悉的公司外,更有自己創業的,也有曾在國外工作的。 現在他們分別在design house、EDA vendor、bio tech公司、foundry擔任各種主管的職務。 歡迎各位同學來聆聽他們的故事及提出你們對 climbing up the career ladder 之相關問題。



邱仕文 執行長/世創生物科技(股)公司

徐孟楷 經理/台積電

張光漢 Section Manager/奕景科技

陳世梁 經理/聯發科技

劉文皓 Senior Software Architect/Cadence Design Systems




邱仕文  世創生物科技股份有限公司/執行長

學歷: 國立清華大學電機博士
經歷: 國立清華大學積體電路中心 博士後研究員

邱仕文博士在求學期間即投入電子鼻系統開發及應用,致力將電子資訊與生命科學整合,將仿生嗅覺應用於呼吸相關的疾病檢測,其研究包含究嗅覺微型感測晶片、微型化氣體感測晶片、演算法等。取得博士學位後致力將所學進行商品化,於2016獲得清大TIX Junior Fellow,並於 2017年創立世創生物科技,將仿生嗅覺與物聯網、應用科學結合,應用在非侵入式疾病診斷、環境監控、食品農業領域等。除獲得天使投資外,也獲到經濟部新創事業獎、破殼而出企業獎、國家新創獎等肯定。



徐孟楷 台積電/經理

Meng-Kai Hsu received the B.S. degrees in electronics engineering and computer science from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, and the Ph.D. degree from the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan, in 2007 and 2012, respectively. He received several awards and honors during his graduate study, including the 1st place of ACM/IEEE Design Automation Conference (DAC) Routability-Driven Placement Contest in 2012 and a Best Paper Award from Taiwan IC Design (TICD) Society. He is currently a Manager of the Design Flow Development Department, Design and Technology Platform, Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Taiwan, and is in charge of advanced technology assessment and physical design enablement especially on mobile and high-performance computing platform. Dr. Hsu currently holds more than 15 U.S. patents.



張光漢  Brillnics Inc.奕景科技/Section Manager

Kwuang-Han Chang received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, in 2011 and 2018, respectively. During his Ph.D studies, he developed analog-to-digital conversion algorithm, methodology, and optimization, and high-speed high-resolution analog-to-digital converters (ADCs).

Since October 2018, he has been with Brillnics Inc., Hsinchu, Taiwan, where he is currently a Section Manager leading digital pixel sensor (DPS) CMOS image sensor (CIS) and developing column/pixel parallel ADCs.

Dr. Chang received NOVATEK Fellowship from 2016 to 2018 and Taiwan IC Design Society (TICD) outstanding Ph.D dissertation award in 2020.



陳世梁  聯發科技/經理

聯發科技, Senior Department Manager (2011~)
數位設計流程 (Digital Design Flow)
design constraints verification and platform management
synthesis and logic equivalent checking
Ethernet IC design flow development

旺宏科技, Engineer (2001~2005)
微控制器晶片設計 (Microcontroller)
智慧卡晶片設計 (Smart Card IC)

清華大學資訊工程所, PhD.
Digital chaotic-systems for security communications
Error-Correction-Code design for flash memories
Low-power ATPG



劉文皓  Cadence Design Systems Senior/Software Architect

Wen-Hao Liu, received his Ph.D. degree in Computer Science from National Chiao Tung University, Taiwan in 2013. His research interests include routing, placement, clock synthesis and logic synthesis. Wen-Hao has published more than 30 papers and 15 patents in these fields, and he has served on the technical program committee of DAC, ICCAD, ISPD, and ASPDAC. Currently, Wen-Hao works at Cadence as a senior software architect and is leading a 3D-IC team in Taiwan. He is the main developer of the next-generation routing engines used in multiple Cadence’s tools, and he has involved in the technology node enablement for 16nm, 10nm, 7nm, 5nm, and 3nm.

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