Tutorials

The Future DNN Accelerator Design Paradigm Deep Neural Network on Chip (DNNoC)

陳坤志 Kun-Chih Chen

國立中山大學資工系 副教授

Abstract

Deep Neural Networks (DNN) have shown significant advantages in many domains such as pattern recognition, prediction, and control optimization. The edge computing demand has motivated many computing platforms to accelerate DNN operations in the Internet-of-Things era. The most common platforms are CPU, GPU, ASIC, and FPGA. However, these platforms suffer from low performance (i.e., CPU and GPU), large power consumption (i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibility at runtime (i.e., FPGA and ASIC). In recent years, Network-on-Chip-based (NoC-based) DNN has become an emerging design paradigm because the NoC interconnection can help to reduce the off-chip memory accesses while offering better scalability and flexibility. This talk will share three novel NoC-based DNN design paradigms: 1) homogeneous DNNoC design methodology, 2) heterogeneous DNNoC design methodology, and 3) reconfigurable DNNoC design methodology, which leverage the DNN accelerator design in the future.

Biography

Kun-Chih (Jimmy) Chen received his PhD degree from Nation Taiwan University, Taiwan (NTU), in Graduate Institute of Electronics Engineering (GIEE) in 2013. He is currently an Associate Professor of Computer Science and Engineering Department of National Sun Yat-sen University. His research interests include Multiprocessor SoC (MPSoC) design, Neural network learning algorithm design, Reliable system design, and VLSI/CAD design. Dr. Chen received the Best Paper Award of VLSI-DAT’14, Best Paper Award of IJCC’16, Best PhD Dissertation Award of IEEE Taipei Section, Taiwan Comprehensive University System (TCUS) Young Scholar Innovation Distinction Award, Best Student Paper Award of IEEE ISCAS’20, IEEE Tainan Section Best Young Professional Member Award, Exploration Research Award of Pan Wen Yuan Foundation, Taiwan IC Design (TICD) Society Outstanding Young Scholar Award, and Chinese Institute of Electrical Engineering (CIEE) Outstanding Youth Electrical Engineer Award. Dr. Chen serves as the referee of many IEEE journals and conferences, including TC, TPDS, TCAS-I, ISCAS, ICASSP, VLSI-DAT, etc. Dr. Chen has served as the Guest Editor of Journal of Systems Architecture (JSA), Nano Communication Network (NanoComNet), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS). Besides, he serves as a Technical Program Committee (TPC) chair of the International Workshop on Network on Chip Architectures (NoCArc) in 2018 and the General Chair of the same workshop in 2019. He is an IEEE senior member, ACM member, APSIPA member, life member of Chinese Institute of Electrical Engineering (CIEE) and Taiwan IC Design (TICD) Society.